A conventional SRAM cell is comprised of first and second driving transistors whose drain-source paths are respectively connected between first and second storage nodes and ground, first and second load elements connected between the first and second storage nodes and power supply, respectively, first and second switching transistors whose drain-source paths are respectively connected between the first and second storage nodes and a pair of data lines (or bit lines). Gates of the first and second driving transistors are connected to the second and first storage nodes, respectively, and gates of the first and second switching transistors are connected to a word line.
SRAM cells may generally be classified according to the manufacturing configuration of the load elements used in the cells. A high resistance SRAM cell uses as load elements layers of high-resistance material such as polycrystalline silicon (typically called "polysilicon") on an insulating layer over a semiconductor substrate in which the first and second driving transistors and the first and second switching transistors are formed. A thin-film SRAM cell uses as load elements thin-film transistors on an insulating layer over the semiconductor substrate on which the four transistors are formed. In a CMOS SRAM cell, first and second load transistors complementary to the first and second driving transistors are formed on the semiconductor substrate together with the other transistors. The CMOS SRAM cell is generally called a full CMOS SRAM cell.
The full CMOS SRAM cell has various advantages of lower standby current, higher operating speed, greater operational stability, greater alpha-particle immunity at a low power supply voltage, as compared with the high resistance and thin-film transistor SRAM cells. As a result, the full CMOS SRAM cell may be widely used in the fields of cache memory for personal computers, nonvolatile buffer memory for direct access storage devices and storage devices for logic LSI and microprocessors. However, a drawback to the full CMOS SRAM cell is that its area is too large to realize a high-density SRAM.
One prior art approach to reducing the cell area in a full CMOS SRAM cell is disclosed in U.S. Pat. No. 5,521,860. This SRAM cell includes first and second driving transistors, first and second load transistors and first and second switching transistors which are respectively arranged symmetrical with respect to a center point in a cell region. The first and second driving transistors and the first and second switching transistors are of n-channel type, and the first and second load transistors are of p-channel type. First and second word lines serving as gate electrodes of the first and second switching transistors are arranged parallel to each other. A first intra-cell connection serving as gate electrodes of the first driving transistor and the first load transistor is connected to drain regions of the second driving transistor and the second load transistor, and a second intra-cell wiring serving as gate electrodes of the second driving transistor and the second load transistor is connected to drain regions of the first driving transistor and the first load transistor. The first and second intra-cell wirings are arranged parallel to each other between the first and second word lines so as to be perpendicular to the word lines. Two ground connections connected to source regions of the first and second driving transistors and a power supply connection connected to source regions of the first and second load transistors are arranged over the word lines and the first and second intra-cell wirings interposing an insulating layer.
However, since the first and second intra-cell wirings and the first and second word lines are arranged at the same level, and the first and second intra-cell wirings are spaced apart so as to be perpendicular to the first and second word lines and to be arranged between the first and second word lines, this prior SRAM cell has a large aspect ratio, i.e., the ratio of longitudinal length to lateral length of cell region. Therefore, a length of each of the bit lines perpendicular to the word lines increases, thereby increasing resistance and parasitic capacitance of each of the bit lines. This problem hinders reading and writing data from and into the memory cell at high speed.
Furthermore, since two ground connections and a power supply connection therebetween are arranged on the insulating layer, reducing the longitudinal length of the cell decreases a width of each of the ground and power supply connections, thereby causing the resistance of each connection to increase. This can result in malfunction of the cell during reading or writing operation due to the voltage drop caused by the increase in resistances of the connections. Therefore, the extent to which the cell size can be scaled down is limited.